Fabricating and Aligning Silicon Nanowires to Investigate Size Dependence for Quantum Confinement and Electronic Transport Analysis Section

The fabrication and understanding of the fundamental properties of well-defined one-dimensional structures are critical towards the development of nanostructures, nanomaterials, and developing nanotechnology. One-dimensional nanostructures can address basic issues about size and dimensionality in applications such as photonics [1,2], nanoelectronics [3,4], nanostructured materials [5,6], and material composites [7,8]. In addition, these structures can efficiently transport electrons and excitons, making them ideal for molecular-scale electronic architectures. Silicon devices have become essential in many current technology devices. As the miniaturization of transistors and circuits continue to progress, the need to wire and connect electronic components become crucial in order for microelectronics to scale down to nanoelectronics. Although nanoscale silicon devices [9,10] as well as wires to connect [11-13] and array [14-16] them have been in development, many obstacles still await. Devices need to be connected to one another; wires, looped and tangled, need to be straightened for circuitry, arrayed wires lack uniform spacing and sometimes the ability to be connected to macro-scale devices. We attempt to address some of the fundamental problems in nanoscale electronics. Specifically, we propose a strategy to fabricate and align silicon nanowires – to directly specify nanoscale wire diameter (as low as 5 nm), align them, and measure the associated electronic characteristics. The strategy has two unique characteristics. First, the nanowires are perfectly aligned during fabrication. Second, the strategy will enable a simple, rapid, and direct manner to explore nanoscale electronic properties of the nanowires. The method will combine “top down” approaches, such as electron beam (ebeam) lithography and plasma-assisted dry etching, with a “bottom-up” approach, such as molecular beam epitaxy (MBE), to fabricate, align, and array nanowires. E-beam lithography and plasma etching will pattern and etch nanometer-sized channels, as small as 5 nm wide, in a thin film, providing a fast and simple technique to create nanometer-sized dimensions on a substrate. MBE will then grow single crystal nanowires in each channel. Since MBE uses a variety of materials for epitaxial growth, metallic and semiconducting nanowires can be deposited onto the substrate. All nanowires will be extensively characterized and analyzed for purity using techniques such as high-resolution transmission electron microscopy (HR-TEM), X-Ray diffraction (XRD), field emission scanning electron microscopy (FE-SEM), and energy dispersive X-Ray spectroscopy (EDX). Then, etching and evaporating electrodes at the ends of each nanowire will individually address each nanowire wire. Electrical properties on the nanoscale (10 nm) regime can then be investigated. By combining these two design paradigms, this proposed strategy will provide controlled wire growth on the atomic scale. The fabricated nanowires will be used to investigate the role of dimensionality and size for electron transport and quantum confinement in nanostructures to further understanding of nanoscale phenomena.